We present a low-power design method that utilizes the multiple supply voltages. The proposed method reduces the power consumption of random logic circuits by 47% on the average, with up to 15% area overhead, by the combination of `Clustered Voltage Scaling (CVS) scheme' and `Row by Row optimized Power Supply (RRPS) scheme'. By the CVS scheme, the optimal netlist, that uses the minimized number of the level converters and the maximized number of the low Vdd gates under the timing constraints, is generated. To avoid the wiring resource consumption and the increase of the interconnect delay caused by the layout constraints of the multiple-supply-voltage design, a new power bus wiring scheme called `RRPS scheme' is proposed. The proposed method is applied to a media processor chip MpactTM and achieved the above mentioned results. In this paper, the emphasis is put on the interrelation between the generation of the two-supply-voltage netlist with the CVS scheme and the layout technology, such as the power supply scheme and the placement of the multiple-supply- voltage gates. The clocking scheme for the multiple supply voltages is also discussed.
|出版ステータス||Published - 1997 1月 1|
|イベント||Proceedings of the 1997 International Symposium on Low Power Electronics and Design - Monterey, CA, USA|
継続期間: 1997 8月 18 → 1997 8月 20
|Other||Proceedings of the 1997 International Symposium on Low Power Electronics and Design|
|City||Monterey, CA, USA|
|Period||97/8/18 → 97/8/20|
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