Low-power design methodology and applications utilizing dual supply voltages

Kimiyoshi Usami, Mutsunori Igarashi

研究成果: Conference contribution

30 引用 (Scopus)

抜粋

This paper describes a gate-level power minimization methodology using dual supply voltages. Gates and flip-flops off the critical paths are made to operate at the reduced supply voltage to save power. Core technologies are dual-V DD circuit synthesis and P&R. We give a brief overview on existing low-power EDA technologies as background and discuss advantages and challenges of the dual-VDD approach. Through real design examples, we will show that the approach reduces power effectively while keeping the performance at negligible area overhead.

元の言語English
ホスト出版物のタイトルProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
ページ123-128
ページ数6
DOI
出版物ステータスPublished - 2000
外部発表Yes
イベント2000 Asia and South Pacific Design Automation Conference, ASP-DAC 2000 - Yokohama
継続期間: 2000 1 252000 1 28

Other

Other2000 Asia and South Pacific Design Automation Conference, ASP-DAC 2000
Yokohama
期間00/1/2500/1/28

    フィンガープリント

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design

これを引用

Usami, K., & Igarashi, M. (2000). Low-power design methodology and applications utilizing dual supply voltages. : Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC (pp. 123-128) https://doi.org/10.1145/368434.368590