Low-power design methodology and applications utilizing dual supply voltages

Kimiyoshi Usami, Mutsunori Igarashi

研究成果: Conference contribution

31 被引用数 (Scopus)

抄録

This paper describes a gate-level power minimization methodology using dual supply voltages. Gates and flip-flops off the critical paths are made to operate at the reduced supply voltage to save power. Core technologies are dual-V DD circuit synthesis and P&R. We give a brief overview on existing low-power EDA technologies as background and discuss advantages and challenges of the dual-VDD approach. Through real design examples, we will show that the approach reduces power effectively while keeping the performance at negligible area overhead.

本文言語English
ホスト出版物のタイトルProceedings of the 2000 Asia and South Pacific Design Automation Conference, ASP-DAC 2000
ページ123-128
ページ数6
DOI
出版ステータスPublished - 2000
外部発表はい
イベント2000 Asia and South Pacific Design Automation Conference, ASP-DAC 2000 - Yokohama, Japan
継続期間: 2000 1 252000 1 28

出版物シリーズ

名前Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Conference

Conference2000 Asia and South Pacific Design Automation Conference, ASP-DAC 2000
CountryJapan
CityYokohama
Period00/1/2500/1/28

ASJC Scopus subject areas

  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

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