Low-power design technique for ASICs by partially reducing supply voltage

Kimiyoshi Usami; Takashi Ishikawa; Masahiro Kanazawa; Hiroko Kotani

Low-power design technique for ASICs by partially reducing supply voltage

Kimiyoshi Usami, Takashi Ishikawa, Masahiro Kanazawa, Hiroko Kotani

研究成果: Conference article › 査読

抄録

In this paper, we discuss power reduction by comparing two different design techniques targeting low-power ASICs: clustered voltage scaling (CVS) and gate resizing. The CVS is a technique to reduce supply voltage partially, allowing to reduce power without performance degradation. As a result of applying to real gate-array circuits, the CVS reduced power by 30-60% even at dominant wire capacitance, while the gate re-sizing got less effective. The CVS is considered to be a key technique toward deep sub-micron age, in which the wire capacitance will be further dominant.

本文言語	English
ページ（範囲）	301-304
ページ数	4
ジャーナル	Proceedings of the Annual IEEE International ASIC Conference and Exhibit
出版ステータス	Published - 1996 1 1
外部発表	はい
イベント	Proceedings of the 1996 9th Annual IEEE International ASIC Conference and Exhibit - Rochester, NY, USA 継続期間: 1996 9 23 → 1996 9 27

ASJC Scopus subject areas

Electrical and Electronic Engineering

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引用スタイル

@article{be8267a4f6574834910ca45d2249c760,

title = "Low-power design technique for ASICs by partially reducing supply voltage",

abstract = "In this paper, we discuss power reduction by comparing two different design techniques targeting low-power ASICs: clustered voltage scaling (CVS) and gate resizing. The CVS is a technique to reduce supply voltage partially, allowing to reduce power without performance degradation. As a result of applying to real gate-array circuits, the CVS reduced power by 30-60% even at dominant wire capacitance, while the gate re-sizing got less effective. The CVS is considered to be a key technique toward deep sub-micron age, in which the wire capacitance will be further dominant.",

author = "Kimiyoshi Usami and Takashi Ishikawa and Masahiro Kanazawa and Hiroko Kotani",

year = "1996",

month = jan,

day = "1",

language = "English",

pages = "301--304",

journal = "Proceedings of the Annual IEEE International ASIC Conference and Exhibit",

issn = "1063-0988",

note = "Proceedings of the 1996 9th Annual IEEE International ASIC Conference and Exhibit ; Conference date: 23-09-1996 Through 27-09-1996",

}

TY - JOUR

T1 - Low-power design technique for ASICs by partially reducing supply voltage

AU - Usami, Kimiyoshi

AU - Ishikawa, Takashi

AU - Kanazawa, Masahiro

AU - Kotani, Hiroko

PY - 1996/1/1

Y1 - 1996/1/1

N2 - In this paper, we discuss power reduction by comparing two different design techniques targeting low-power ASICs: clustered voltage scaling (CVS) and gate resizing. The CVS is a technique to reduce supply voltage partially, allowing to reduce power without performance degradation. As a result of applying to real gate-array circuits, the CVS reduced power by 30-60% even at dominant wire capacitance, while the gate re-sizing got less effective. The CVS is considered to be a key technique toward deep sub-micron age, in which the wire capacitance will be further dominant.

AB - In this paper, we discuss power reduction by comparing two different design techniques targeting low-power ASICs: clustered voltage scaling (CVS) and gate resizing. The CVS is a technique to reduce supply voltage partially, allowing to reduce power without performance degradation. As a result of applying to real gate-array circuits, the CVS reduced power by 30-60% even at dominant wire capacitance, while the gate re-sizing got less effective. The CVS is considered to be a key technique toward deep sub-micron age, in which the wire capacitance will be further dominant.

UR - http://www.scopus.com/inward/record.url?scp=0029726316&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0029726316&partnerID=8YFLogxK

M3 - Conference article

AN - SCOPUS:0029726316

SP - 301

EP - 304

JO - Proceedings of the Annual IEEE International ASIC Conference and Exhibit

JF - Proceedings of the Annual IEEE International ASIC Conference and Exhibit

SN - 1063-0988

T2 - Proceedings of the 1996 9th Annual IEEE International ASIC Conference and Exhibit

Y2 - 23 September 1996 through 27 September 1996

ER -