TY - JOUR
T1 - Low-power design technique for ASICs by partially reducing supply voltage
AU - Usami, Kimiyoshi
AU - Ishikawa, Takashi
AU - Kanazawa, Masahiro
AU - Kotani, Hiroko
PY - 1996/1/1
Y1 - 1996/1/1
N2 - In this paper, we discuss power reduction by comparing two different design techniques targeting low-power ASICs: clustered voltage scaling (CVS) and gate resizing. The CVS is a technique to reduce supply voltage partially, allowing to reduce power without performance degradation. As a result of applying to real gate-array circuits, the CVS reduced power by 30-60% even at dominant wire capacitance, while the gate re-sizing got less effective. The CVS is considered to be a key technique toward deep sub-micron age, in which the wire capacitance will be further dominant.
AB - In this paper, we discuss power reduction by comparing two different design techniques targeting low-power ASICs: clustered voltage scaling (CVS) and gate resizing. The CVS is a technique to reduce supply voltage partially, allowing to reduce power without performance degradation. As a result of applying to real gate-array circuits, the CVS reduced power by 30-60% even at dominant wire capacitance, while the gate re-sizing got less effective. The CVS is considered to be a key technique toward deep sub-micron age, in which the wire capacitance will be further dominant.
UR - http://www.scopus.com/inward/record.url?scp=0029726316&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0029726316&partnerID=8YFLogxK
M3 - Conference article
AN - SCOPUS:0029726316
SP - 301
EP - 304
JO - Proceedings of the Annual IEEE International ASIC Conference and Exhibit
JF - Proceedings of the Annual IEEE International ASIC Conference and Exhibit
SN - 1063-0988
T2 - Proceedings of the 1996 9th Annual IEEE International ASIC Conference and Exhibit
Y2 - 23 September 1996 through 27 September 1996
ER -