Low-power design technique for ASICs by partially reducing supply voltage

Kimiyoshi Usami, Takashi Ishikawa, Masahiro Kanazawa, Hiroko Kotani

研究成果: Conference article

24 引用 (Scopus)

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In this paper, we discuss power reduction by comparing two different design techniques targeting low-power ASICs: clustered voltage scaling (CVS) and gate resizing. The CVS is a technique to reduce supply voltage partially, allowing to reduce power without performance degradation. As a result of applying to real gate-array circuits, the CVS reduced power by 30-60% even at dominant wire capacitance, while the gate re-sizing got less effective. The CVS is considered to be a key technique toward deep sub-micron age, in which the wire capacitance will be further dominant.

元の言語English
ページ(範囲)301-304
ページ数4
ジャーナルProceedings of the Annual IEEE International ASIC Conference and Exhibit
出版物ステータスPublished - 1996 1 1
イベントProceedings of the 1996 9th Annual IEEE International ASIC Conference and Exhibit - Rochester, NY, USA
継続期間: 1996 9 231996 9 27

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ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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