TY - JOUR
T1 - Low-power technique for on-chip memory using biased partitioning and access concentration
AU - Kawabe, Naoyuki
AU - Usami, Kimiyoshi
PY - 2000/1/1
Y1 - 2000/1/1
N2 - In this paper, we propose a low-power technique for on-chip memory using biased partitioning and access concentration (BPAC) technique. Memory array is partitioned into different size of two sub-arrays by inserting transfer-gate into a bit-line. When smaller array is accessed, larger array is electrically separated to reduce power. In addition, we perform code motion so that the code with higher access frequency be made to concentrate in the smaller sub-array. We applied BPAC technique to instruction memory of MPEG4 Codec LSI. Power consumption was reduced by 40%.
AB - In this paper, we propose a low-power technique for on-chip memory using biased partitioning and access concentration (BPAC) technique. Memory array is partitioned into different size of two sub-arrays by inserting transfer-gate into a bit-line. When smaller array is accessed, larger array is electrically separated to reduce power. In addition, we perform code motion so that the code with higher access frequency be made to concentrate in the smaller sub-array. We applied BPAC technique to instruction memory of MPEG4 Codec LSI. Power consumption was reduced by 40%.
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M3 - Conference article
AN - SCOPUS:0033711828
SP - 275
EP - 278
JO - Proceedings of the Custom Integrated Circuits Conference
JF - Proceedings of the Custom Integrated Circuits Conference
SN - 0886-5930
T2 - CICC 2000: 22nd Annual Custom Integrated Circuits Conference
Y2 - 21 May 2000 through 24 May 2000
ER -