抜粋
In this paper, we propose a low-power technique for on-chip memory using biased partitioning and access concentration (BPAC) technique. Memory array is partitioned into different size of two sub-arrays by inserting transfer-gate into a bit-line. When smaller array is accessed, larger array is electrically separated to reduce power. In addition, we perform code motion so that the code with higher access frequency be made to concentrate in the smaller sub-array. We applied BPAC technique to instruction memory of MPEG4 Codec LSI. Power consumption was reduced by 40%.
| 元の言語 | English |
|---|---|
| ホスト出版物のタイトル | Proceedings of the Custom Integrated Circuits Conference |
| 出版者 | IEEE |
| ページ | 275-278 |
| ページ数 | 4 |
| 出版物ステータス | Published - 2000 |
| 外部発表 | Yes |
| イベント | CICC 2000: 22nd Annual Custom Integrated Circuits Conference - Orlando, FL, USA 継続期間: 2000 5 21 → 2000 5 24 |
Other
| Other | CICC 2000: 22nd Annual Custom Integrated Circuits Conference |
|---|---|
| 市 | Orlando, FL, USA |
| 期間 | 00/5/21 → 00/5/24 |
フィンガープリント
ASJC Scopus subject areas
- Electrical and Electronic Engineering
これを引用
Kawabe, N., & Usami, K. (2000). Low-power technique for on-chip memory using biased partitioning and access concentration. ： Proceedings of the Custom Integrated Circuits Conference (pp. 275-278). IEEE.