Low-power technique for on-chip memory using biased partitioning and access concentration

Naoyuki Kawabe, Kimiyoshi Usami

研究成果: Conference contribution

6 引用 (Scopus)

抜粋

In this paper, we propose a low-power technique for on-chip memory using biased partitioning and access concentration (BPAC) technique. Memory array is partitioned into different size of two sub-arrays by inserting transfer-gate into a bit-line. When smaller array is accessed, larger array is electrically separated to reduce power. In addition, we perform code motion so that the code with higher access frequency be made to concentrate in the smaller sub-array. We applied BPAC technique to instruction memory of MPEG4 Codec LSI. Power consumption was reduced by 40%.

元の言語English
ホスト出版物のタイトルProceedings of the Custom Integrated Circuits Conference
出版者IEEE
ページ275-278
ページ数4
出版物ステータスPublished - 2000
外部発表Yes
イベントCICC 2000: 22nd Annual Custom Integrated Circuits Conference - Orlando, FL, USA
継続期間: 2000 5 212000 5 24

Other

OtherCICC 2000: 22nd Annual Custom Integrated Circuits Conference
Orlando, FL, USA
期間00/5/2100/5/24

    フィンガープリント

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

これを引用

Kawabe, N., & Usami, K. (2000). Low-power technique for on-chip memory using biased partitioning and access concentration. : Proceedings of the Custom Integrated Circuits Conference (pp. 275-278). IEEE.