This paper discusses the selection of the optimal device for LSI implementation of Viterbi decoder. The relation between the available number of gates and the performance of the decoder is described clearly. A method of reducing the number of gates for low‐and high‐speed LSI decoders, as well as their major performance, is described. To reduce the cost for LSI as the system LSI, it is important to maintain the versatility of the developed LSI. From such a viewpoint, general‐purpose, a highly efficient Viterbi decoder is considered by using a ROM and two kinds of LSI. The construction and the performance are discussed, aiming at an LSI implementation. The developed LSI operates at the frequency of 25 MHz or higher. It is applicable generally to the error correction with (N −1)/N coding rate. Compared with the Viterbi decoder using the same kind of LSI, the proposed LSI minimizes the number of chips and improves the speed by a factor of 1.5. By this elaboration, the device can drastically be reduced in size and cost, leading to an easier realization of a high‐speed, highly efficient and high‐gain error‐correcting system.
|ジャーナル||Electronics and Communications in Japan (Part III: Fundamental Electronic Science)|
|出版ステータス||Published - 1990|
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