Material and process challenges for interconnects in nanoelectronics era

Cu/low-k interconnects have been used in LSI fabrication. However, several difficult challenges need to be overcome for 22-nm node devices and beyond. These challenges include an increase in resistivity, degradation of the electromigration reliability, and the low mechanical strength of low-k dielectrics. To overcome these problems, it is essential to not only improve Cu/low-k fabrication processes but also to develop alternative approaches based on emerging technologies such as 3D interconnects, nanocarbon interconnects, and optical interconnects. This paper reviews the problems and potential solutions, and describes approaches such as supercritical (SC) annealing for grain growth enhancement, CoWP caps for electromigration (EM) reliability improvement, and electroless barrier deposition for ultrathin barrier layer.