Measurement of SSO noise and PDN impedance of 3D SiP with 4k-IO widebus structure

Yosuke Tanaka, Hiroki Takatani, Haruya Fujita, Yoshiaki Oizono, Yoshitaka Nabeshima, Toshio Sudo, Atsushi Sakai, Shiro Uchiyama, Hiroaki Ikeda

研究成果: Conference contribution

3 被引用数 (Scopus)

抄録

Simultaneous switching output buffer (SSO) noise and impedance of power distribution network (PDN) for a 3D systemin package (SiP) with 4k-IO widebus structure has been investigated. The 3D SiP consisted of 3 stacked chips and an organic interposer. These three chips were a memory chip on the top, a silicon interposer in the middle, and a logic chip on the bottom. The size of each chip was the same, and 9.93 mm by 9.93 mm. More than 4096 of through silicon vias (TSV's) were formed to the silicon interposer. Next, these 3 stacked chips were assembled on the organic interposer, whose size was 26 mm by 26mm. SSO noise is one of critical issues for the 3D SiP with 4k-IO widebus structure. So, the SSO noise was measured in the miniIO power supply system in an evaluation board. Furthermore the PDN impedance for each chip was measured by direct contact method. Then, the total PDN impedance was synthesized to confirm the anti-resonance peak of it.

本文言語English
ホスト出版物のタイトル2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2012
ページ91-94
ページ数4
DOI
出版ステータスPublished - 2012 12 1
イベント2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2012 - Tempe, AZ, United States
継続期間: 2012 10 212012 10 24

出版物シリーズ

名前2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2012

Conference

Conference2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2012
CountryUnited States
CityTempe, AZ
Period12/10/2112/10/24

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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