Multi bit PWMDAC with multi delay inverter

Daichi Kodama, Eri Ioka, Yasuyuki Matsuya

研究成果: Article査読

1 被引用数 (Scopus)

抄録

The conventional local PWM-DAC for the ΔΣ D/A converter generates the PWM wave by dividing the clock signal. In this method, the sampling speed is decreased greatly by increasing the resolution. In this paper, we propose a new PWM-DAC with the Multi-Delay inverter. This DAC does not require the dividing clock as the conventional PWM-DAC. As simulation results, we show that the 5-th order ΔΣ D/A converter with the propose DAC achieves the S/N of 130 dB at the MOS transistor threshold voltage deviation of 100 mV.

本文言語English
ページ(範囲)239-244
ページ数6
ジャーナルIEEJ Transactions on Electronics, Information and Systems
133
2
DOI
出版ステータスPublished - 2013
外部発表はい

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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