The technology, which is suitable for submicron VLSI, features bird's beak free, planar surface, low defect generation, and is adaptable to any isolation width from submicron to very large dimensions. The key process steps consist of filling the trench with polysilicon to half of the trench depth by utilizing photoresist etch back, and subsequent full oxidation of the recessed polysilicon to fill the trench by the oxide. Device characteristics examined experimentally are equivalent to those of LOCOS isolated devices. The feasibility of this technology has been verified successfully by fabricating a 64K bit DRAM.
|ジャーナル||Technical Digest - International Electron Devices Meeting|
|出版ステータス||Published - 1984 12月 1|
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