Nonvolatile power gating with MTJ based nonvolatile flip-flops for a microprocessor

Masaru Kudo, Kimiyoshi Usami

研究成果: Conference contribution

1 引用 (Scopus)

抜粋

This paper describes an approach to combine spintransfer torque Magnetic Tunnel Junction (MTJ) based non-volatile flip-flops (NVFFs) with power gating techniques to enable anytime power-off and instant power-on. We analyzed the NVFFs which are expected to realize nonvolatile power gating (NVPG) for a microprocessor. We evaluated the NVFFs by the area, the performance and the energy dissipation. We also investigated effectiveness of NVPG that combines the NVFFs with the 32-bit microprocessor core. The simulation results showed that the NVPG reduced more energy dissipation when the idle time of the microprocessor is longer than 5ms at 25°C as compared with the conventional SRAM-backup scheme. Additionally, the NVPG was able to reduce more energy dissipation at higher temperature.

元の言語English
ホスト出版物のタイトルNVMSA 2017 - 6th IEEE Non-Volatile Memory Systems and Applications Symposium
出版者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子版)9781538617687
DOI
出版物ステータスPublished - 2017 10 10
イベント6th IEEE Non-Volatile Memory Systems and Applications Symposium, NVMSA 2017 - Hsinchu, Taiwan, Province of China
継続期間: 2017 8 162017 8 18

出版物シリーズ

名前NVMSA 2017 - 6th IEEE Non-Volatile Memory Systems and Applications Symposium

Other

Other6th IEEE Non-Volatile Memory Systems and Applications Symposium, NVMSA 2017
Taiwan, Province of China
Hsinchu
期間17/8/1617/8/18

ASJC Scopus subject areas

  • Hardware and Architecture

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  • これを引用

    Kudo, M., & Usami, K. (2017). Nonvolatile power gating with MTJ based nonvolatile flip-flops for a microprocessor. : NVMSA 2017 - 6th IEEE Non-Volatile Memory Systems and Applications Symposium [8064472] (NVMSA 2017 - 6th IEEE Non-Volatile Memory Systems and Applications Symposium). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/NVMSA.2017.8064472