Novel Viterbi Decoder VLSI Implementation and its Performance

Shuji Kubota, Shuzo Kato, Tsunehachi Ishitani

研究成果: Article査読

34 被引用数 (Scopus)

抄録

This paper presents an advanced, high-speed, and universal-coding-rate Viterbi decoder VLSI implementation. Two novel circuit design schemes have been proposed: “scarce state transition (SST)” and “direct high-coding-rate convolutional code generation and variable-rate Viterbi decoding.” SST makes it possible to omit the final decision circuit and to reduce the required path memory length without degrading Pe performance. Moreover, the power consumption of the SST Viterbi decoder is significantly reduced when implemented as a CMOS devices. These features overcome the speed limits of high-speed and high-coding-gain Viterbi decoder VLSI’s in the rate one-half mode imposed by the thermal limitation. Moreover, the proposed direct high-coding-rate convolutional code generation and variable-rate Viterbi decoding scheme make it possible to realize a simple and variable coding-rate forward-error-correction circuit by changing only the branch metric calculation ROM tables. By employing these schemes, high-speed (25 Mb/s) and universal-coding-rate Viterbi decoder VLSI’s have been developed. Experimental results employing developed Viterbi decoder VLSI’s confirm satisfactoryPe performance and high operation speeds under various conditions, for example, AWGN, cochannel interference, and adjacent channel interference environments.

本文言語English
ページ(範囲)1170-1178
ページ数9
ジャーナルIEEE Transactions on Communications
41
8
DOI
出版ステータスPublished - 1993 8
外部発表はい

ASJC Scopus subject areas

  • 電子工学および電気工学

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