Numerical analysis of GaAs MESFETs with p-buffer layer on semi-insulating substrate including deep traps

Kazushige Horio, H. Yanai

研究成果: Article

2 引用 (Scopus)

抄録

Numerical analysis of GaAs MESFETs with a p-buffer layer on the semi-insulating substrate is presented in which impurity compensation by traps is included. Using a p-buffer layer is shown to be effective in minimizing the short-channel effects as in the case of using a substrate with high density of traps.

元の言語English
ページ(範囲)86-88
ページ数3
ジャーナルElectronics Letters
25
発行部数2
出版物ステータスPublished - 1989 1 1

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Buffer layers
Numerical analysis
Substrates
Impurities
Compensation and Redress

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

これを引用

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