Numerical Simulation of GaAs MESFET's with a p-Buffer Layer on the Semi-Insulating Substrate Compensated by Deep Traps

Kazushige Horio, Yasuji Fuseya, Hiroyuki Kusuki, Hisayoshi Yanai

研究成果: Article査読

11 被引用数 (Scopus)

抄録

Numerical simulation of GaAs MESFETs with a p-buffer layer on the semi-insulating substrate is performed in which impurity compensation by traps in the substrate is considered. It is shown that the use of a thicker p-buffer layer results in lower device current due to the formation of a steeper barrier at the channel-substrate interface. It is also shown that in a case with higher acceptor and trap densities in the substrate, the drain current becomes lower due to the decrease in the substrate current. This decrease in the substrate current occurs due to the formation of a negative space-charge layer in the substrate. It is concluded that using a thick p-buffer layer has the same effect as using a substrate with a high density of traps inasmuch as both of them lead to minimizing the short-channel effects in GaAs MESFET's.

本文言語English
ページ(範囲)1371-1379
ページ数9
ジャーナルIEEE Transactions on Microwave Theory and Techniques
37
9
DOI
出版ステータスPublished - 1989 9

ASJC Scopus subject areas

  • Radiation
  • Condensed Matter Physics
  • Electrical and Electronic Engineering

フィンガープリント 「Numerical Simulation of GaAs MESFET's with a p-Buffer Layer on the Semi-Insulating Substrate Compensated by Deep Traps」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

引用スタイル