In a fine-grain leakage saving technique to power gate function units, the efficiency is sensitive to overhead energy dissipating at turning on/off power switches. To get gain in energy savings, the powered-off period has to be longer than the minimum required time i.e. the break-even time (BET). While effectiveness of BET-aware power-gating control has been described in literatures, how to actually detect BET that fluctuates with the temperature and process variation has not been reported so far. This paper proposes an on-chip detection methodology for BET using pMOS/nMOS leakage monitors with MTCMOS circuit structure. We applied this methodology to the leakage monitors and a CPU including a power-gated multiplier implemented in 65nm CMOS technology. Results showed that our methodology detects BET at 5%-17% difference from that of the conventional simulation-based off-line technique.
|ホスト出版物のタイトル||Proceedings of the International Symposium on Low Power Electronics and Design|
|出版物ステータス||Published - 2011|
|イベント||17th IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011 - Fukuoka|
継続期間: 2011 8 1 → 2011 8 3
|Other||17th IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011|
|期間||11/8/1 → 11/8/3|
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