On-chip detection methodology for break-even time of power gated function units

Kimiyoshi Usami, Yuya Goto, Kensaku Matsunaga, Satoshi Koyama, Daisuke Ikebuchi, Hideharu Amano, Hiroshi Nakamura

研究成果: Conference contribution

13 引用 (Scopus)

抜粋

In a fine-grain leakage saving technique to power gate function units, the efficiency is sensitive to overhead energy dissipating at turning on/off power switches. To get gain in energy savings, the powered-off period has to be longer than the minimum required time i.e. the break-even time (BET). While effectiveness of BET-aware power-gating control has been described in literatures, how to actually detect BET that fluctuates with the temperature and process variation has not been reported so far. This paper proposes an on-chip detection methodology for BET using pMOS/nMOS leakage monitors with MTCMOS circuit structure. We applied this methodology to the leakage monitors and a CPU including a power-gated multiplier implemented in 65nm CMOS technology. Results showed that our methodology detects BET at 5%-17% difference from that of the conventional simulation-based off-line technique.

元の言語English
ホスト出版物のタイトルProceedings of the International Symposium on Low Power Electronics and Design
ページ241-246
ページ数6
DOI
出版物ステータスPublished - 2011
イベント17th IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011 - Fukuoka
継続期間: 2011 8 12011 8 3

Other

Other17th IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011
Fukuoka
期間11/8/111/8/3

    フィンガープリント

ASJC Scopus subject areas

  • Engineering(all)

これを引用

Usami, K., Goto, Y., Matsunaga, K., Koyama, S., Ikebuchi, D., Amano, H., & Nakamura, H. (2011). On-chip detection methodology for break-even time of power gated function units. : Proceedings of the International Symposium on Low Power Electronics and Design (pp. 241-246). [5993643] https://doi.org/10.1109/ISLPED.2011.5993643