On-chip power integrity evaluation system

Yoshitaka Nabeshima, Yoshiaki Oizono, Takafumi Okumura, Toshio Sudo

研究成果: Conference contribution

抄録

Power supply disturbance excited by simultaneous switching output (SSO) circuits or core circuits is a serious issue in a system-in-package (SIP), especially in 3D stacked die package, because much more I/O circuits and core circuits excited simultaneously in synchronized with clock edges than the case of single die package. Therefore, decoupling schemes in such SiP's must be carefully designed including on-chip capacitance as well as off-chip capacitance so as to reduce the impedance of power distribution network (PDN) as low as possible up to high frequency range. In this paper, an on-chip power integrity evaluation system has been established using a test chip with both noise generating circuits and monitoring circuits for on-chip power supply noise. On-chip power integrity has been examined and compared for the cases with and without on-chip capacitance and for the various embedded capacitors inside an interposer.

本文言語English
ホスト出版物のタイトルProceedings of the 8th International Workshop on Electromagnetic Compatibility of Integrated Circuits 2011, EMC COMPO 2011
ページ165-169
ページ数5
出版ステータスPublished - 2011 12 1
イベント8th International Workshop on Electromagnetic Compatibility of Integrated Circuits, EMC COMPO 2011 - Dubrovnik, Croatia
継続期間: 2011 11 62011 11 9

出版物シリーズ

名前Proceedings of the 8th International Workshop on Electromagnetic Compatibility of Integrated Circuits 2011, EMC COMPO 2011

Conference

Conference8th International Workshop on Electromagnetic Compatibility of Integrated Circuits, EMC COMPO 2011
国/地域Croatia
CityDubrovnik
Period11/11/611/11/9

ASJC Scopus subject areas

  • ハードウェアとアーキテクチャ

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