Open-loop full CMOS 103 MHz -61 dB THD S/H circuit

Khayrollah Hadidi; Masahiro Sasaki; Tadatoshi Watanabe; Daigo Muramatsu; Takashi Matsumoto

Open-loop full CMOS 103 MHz -61 dB THD S/H circuit

Khayrollah Hadidi, Masahiro Sasaki, Tadatoshi Watanabe, Daigo Muramatsu, Takashi Matsumoto

研究成果: Conference article › 査読

抄録

Based on a real open loop architecture and a cascode-driver CMOS source-follower, we implemented a S/H circuit in a 0.8 μm digital CMOS process. The circuit achieved -61 dB THD at a sampling rate of 103 MHz, while a 1.42 V_p-p 10 MHz input signal was applied. This includes all parasitic loading and transient effect.

本文言語	English
ページ（範囲）	381-383
ページ数	3
ジャーナル	Proceedings of the Custom Integrated Circuits Conference
出版ステータス	Published - 1998 1月 1
イベント	Proceedings of the 1998 IEEE Custom Integrated Circuits Conference - Santa Clara, CA, USA 継続期間: 1998 5月 11 → 1998 5月 14

ASJC Scopus subject areas

電子工学および電気工学

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引用スタイル

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title = "Open-loop full CMOS 103 MHz -61 dB THD S/H circuit",

abstract = "Based on a real open loop architecture and a cascode-driver CMOS source-follower, we implemented a S/H circuit in a 0.8 μm digital CMOS process. The circuit achieved -61 dB THD at a sampling rate of 103 MHz, while a 1.42 Vp-p 10 MHz input signal was applied. This includes all parasitic loading and transient effect.",

author = "Khayrollah Hadidi and Masahiro Sasaki and Tadatoshi Watanabe and Daigo Muramatsu and Takashi Matsumoto",

year = "1998",

month = jan,

day = "1",

language = "English",

pages = "381--383",

journal = "Proceedings of the Custom Integrated Circuits Conference",

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publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "Proceedings of the 1998 IEEE Custom Integrated Circuits Conference ; Conference date: 11-05-1998 Through 14-05-1998",

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T1 - Open-loop full CMOS 103 MHz -61 dB THD S/H circuit

AU - Hadidi, Khayrollah

AU - Sasaki, Masahiro

AU - Watanabe, Tadatoshi

AU - Muramatsu, Daigo

AU - Matsumoto, Takashi

PY - 1998/1/1

Y1 - 1998/1/1

N2 - Based on a real open loop architecture and a cascode-driver CMOS source-follower, we implemented a S/H circuit in a 0.8 μm digital CMOS process. The circuit achieved -61 dB THD at a sampling rate of 103 MHz, while a 1.42 Vp-p 10 MHz input signal was applied. This includes all parasitic loading and transient effect.

AB - Based on a real open loop architecture and a cascode-driver CMOS source-follower, we implemented a S/H circuit in a 0.8 μm digital CMOS process. The circuit achieved -61 dB THD at a sampling rate of 103 MHz, while a 1.42 Vp-p 10 MHz input signal was applied. This includes all parasitic loading and transient effect.

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M3 - Conference article

AN - SCOPUS:0031617340

SN - 0886-5930

SP - 381

EP - 383

JO - Proceedings of the Custom Integrated Circuits Conference

JF - Proceedings of the Custom Integrated Circuits Conference

T2 - Proceedings of the 1998 IEEE Custom Integrated Circuits Conference

Y2 - 11 May 1998 through 14 May 1998

ER -

Open-loop full CMOS 103 MHz -61 dB THD S/H circuit

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ASJC Scopus subject areas

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