Open-loop full CMOS 103 MHz -61 dB THD S/H circuit

Khayrollah Hadidi, Masahiro Sasaki, Tadatoshi Watanabe, Daigo Muramatsu, Takashi Matsumoto

研究成果: Conference article

19 引用 (Scopus)

抜粋

Based on a real open loop architecture and a cascode-driver CMOS source-follower, we implemented a S/H circuit in a 0.8 μm digital CMOS process. The circuit achieved -61 dB THD at a sampling rate of 103 MHz, while a 1.42 Vp-p 10 MHz input signal was applied. This includes all parasitic loading and transient effect.

元の言語English
ページ(範囲)381-383
ページ数3
ジャーナルProceedings of the Custom Integrated Circuits Conference
出版物ステータスPublished - 1998 1 1
イベントProceedings of the 1998 IEEE Custom Integrated Circuits Conference - Santa Clara, CA, USA
継続期間: 1998 5 111998 5 14

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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