Optimal Design for Level-Shifter-Less Approach Using Channel Length Modulation Body Biasing

Tatsuya Watanabe, Kimiyoshi Usami

研究成果: Conference contribution

抄録

A multi-VDD design realizes LSIs to be low power by allowing to use multiple different power supply voltages. In this design, conversion of the voltage amplitude of the signal is necessary. This is usually done by inserting a circuit called a level shifter, between voltage domains as an interface. However, insertion of level shifter has disadvantages in silicon footprint, power consumption, and delays. In this paper, we propose a level-shifter-less approach by increasing channel length. We also propose the optimal design using both channel length modulation and body biasing.

本文言語English
ホスト出版物のタイトルITC-CSCC 2020 - 35th International Technical Conference on Circuits/Systems, Computers and Communications
出版社Institute of Electrical and Electronics Engineers Inc.
ページ223-227
ページ数5
ISBN(電子版)9784885523281
出版ステータスPublished - 2020 7
イベント35th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2020 - Nagoya, Japan
継続期間: 2020 7 32020 7 6

出版物シリーズ

名前ITC-CSCC 2020 - 35th International Technical Conference on Circuits/Systems, Computers and Communications

Conference

Conference35th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2020
CountryJapan
CityNagoya
Period20/7/320/7/6

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Hardware and Architecture
  • Information Systems and Management
  • Electrical and Electronic Engineering

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