PACKAGING TECHNOLOGY FOR HIGH SPEED LOGIC DEVICES.

T. Sudo, A. Iida, K. Yoshihara, T. Miyagi, T. Saito

研究成果: Paper

抜粋

Recent advances in high speed logic ICs have given rise to the need for a new concept in packaging technology. High speed devices such as GaAs digital ICs are expected to operate in high speed and relatively low power dissipation. The authors discuss internal gate-to-gate interconnection wiring energy and external chip-to-chip interconnection energy. GaAs digital ICs have high output impedance, so the high characteristic impedance of transmission lines on the packaging substrate would be advantageous in reducing chip-to-chip interconnection energy and preserving inherent chip speed. On the other hand, the crosstalk induced between adjacent lines becomes greater, so that the optimum condition of the interconnection structure on the packaging substrate will be determined as a tradeoff between the above two factors.

元の言語English
ページ160-164
ページ数5
出版物ステータスPublished - 1984 12 1

ASJC Scopus subject areas

  • Engineering(all)

フィンガープリント PACKAGING TECHNOLOGY FOR HIGH SPEED LOGIC DEVICES.' の研究トピックを掘り下げます。これらはともに一意のフィンガープリントを構成します。

  • これを引用

    Sudo, T., Iida, A., Yoshihara, K., Miyagi, T., & Saito, T. (1984). PACKAGING TECHNOLOGY FOR HIGH SPEED LOGIC DEVICES.. 160-164.