PDN characteristics of 3D-SiP with a wide-bus structure under 4k-IO operations

Atsushi Sakai, Shigeru Yamada, Takashi Kariya, Shiro Uchiyama, Hiroaki Ikeda, Haruya Fujita, Hiroki Takatani, Yosuke Tanaka, Yoshiaki Oizono, Yoshitaka Nabeshima, Toshio Sudo

研究成果: Conference contribution

1 被引用数 (Scopus)

抄録

The 4096 bits wide-bus three-dimensional integration device using through-silicon-vias (TSVs) has been designed and fabricated as a demonstrator for power integrity such as power distribution network (PDN) impedance and simultaneous switching output (SSO) noise characteristics. Anti-resonance peak of total PDN impedance was extracted at around 80 MHz. This result was well coincident with maximum SSO noise frequency at around 75 MHz. Further, SSO noise reduction clocking named phase-shift clock has also been implemented to demonstrate the effectiveness as measurement basis.

本文言語English
ホスト出版物のタイトル2012 2nd IEEE CPMT Symposium Japan, ICSJ 2012
DOI
出版ステータスPublished - 2012 12 1
イベント2012 2nd IEEE CPMT Symposium Japan, ICSJ 2012 - Kyoto, Japan
継続期間: 2012 12 102012 12 12

出版物シリーズ

名前2012 2nd IEEE CPMT Symposium Japan, ICSJ 2012

Conference

Conference2012 2nd IEEE CPMT Symposium Japan, ICSJ 2012
CountryJapan
CityKyoto
Period12/12/1012/12/12

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

フィンガープリント 「PDN characteristics of 3D-SiP with a wide-bus structure under 4k-IO operations」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

引用スタイル