Power gating for FDSOI using dynamically body-biased power switch

Yuichi Kumagai, Masaru Kudo, Kimiyoshi Usami

研究成果: Conference contribution

抄録

We propose a Dynamically Biased Multi Threshold CMOS (DBMT) technique for power gating in FDSOI. In DBMT, effective threshold voltage of a high-Vt power switch transistor is lowered by forward body biasing (FBB) to improve performance at the operation, while it is raised by reverse body biasing (RBB) to further reduce leakage in the sleep state. We applied this technique to a 32-bit multiplier circuit of an experimental CPU Geyser-1 in which the multiplier is power gated at run time in a fine-grained manner during the CPU operation [1]. Simulated results in 65nm FDSOI with thin BOX revealed that the area of the power switch (PS) in DBMT technique can be reduced by 55% as compared to the conventional MTCMOS when suppressing the delay increase due to PS insertion within 10%. DBMT reduces leakage energy of the multiplier considering the energy overhead by up to 55% as compared to the MTCMOS when running application programs.

元の言語English
ホスト出版物のタイトルEUROSOI-ULIS 2015 - 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon
出版者Institute of Electrical and Electronics Engineers Inc.
ページ221-224
ページ数4
ISBN(印刷物)9781479969111
DOI
出版物ステータスPublished - 2015 3 18
イベント2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2015 - Bologna, Italy
継続期間: 2015 1 262015 1 28

Other

Other2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2015
Italy
Bologna
期間15/1/2615/1/28

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Switches
Program processors
Threshold voltage
Application programs
Transistors
Networks (circuits)
Sleep

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

これを引用

Kumagai, Y., Kudo, M., & Usami, K. (2015). Power gating for FDSOI using dynamically body-biased power switch. : EUROSOI-ULIS 2015 - 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (pp. 221-224). [7063813] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ULIS.2015.7063813

Power gating for FDSOI using dynamically body-biased power switch. / Kumagai, Yuichi; Kudo, Masaru; Usami, Kimiyoshi.

EUROSOI-ULIS 2015 - 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon. Institute of Electrical and Electronics Engineers Inc., 2015. p. 221-224 7063813.

研究成果: Conference contribution

Kumagai, Y, Kudo, M & Usami, K 2015, Power gating for FDSOI using dynamically body-biased power switch. : EUROSOI-ULIS 2015 - 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon., 7063813, Institute of Electrical and Electronics Engineers Inc., pp. 221-224, 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2015, Bologna, Italy, 15/1/26. https://doi.org/10.1109/ULIS.2015.7063813
Kumagai Y, Kudo M, Usami K. Power gating for FDSOI using dynamically body-biased power switch. : EUROSOI-ULIS 2015 - 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon. Institute of Electrical and Electronics Engineers Inc. 2015. p. 221-224. 7063813 https://doi.org/10.1109/ULIS.2015.7063813
Kumagai, Yuichi ; Kudo, Masaru ; Usami, Kimiyoshi. / Power gating for FDSOI using dynamically body-biased power switch. EUROSOI-ULIS 2015 - 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon. Institute of Electrical and Electronics Engineers Inc., 2015. pp. 221-224
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