Power integrity improvement by controlling on-die PDN properties

Toshio Sudo, Sho Kiyoshige, Wataru Ichimura, Masahiro Terasaki, Ryota Kobayashi, Genki Kubo, Hiroki Otsuka

研究成果: Conference contribution

抄録

Power integrity has became a serious issue in the advanced CMOS digital systems, because power supply noise must be suppressed to guarantee normal logic operation and its stability. Therefore, chip-package-board co-design has become important by taking into consideration the total impedance seen from the chip. Especially, parallel resonance peaks in the power distribution network (PDN) due to the chip-package interaction induces the unwanted power supply fluctuation, and results in the degradation of signal integrity and electromagnetic interference (EMI). In this paper, three test chips were designed with different on-chip PDN properties. The effects of critical damping condition for the total PDN impedance on power supply noise has been examined by adding different RC circuit to the intrinsic on-die RC circuit of chip. The measurement and analysis of power supply noises for the three test chips showed typical characteristics of oscillatory region and damped regions The critical damping condition against the anti-resonance peak has been proved to be effective to suppress the power supply noise on the chip.

本文言語English
ホスト出版物のタイトルEDAPS 2013 - 2013 IEEE Electrical Design of Advanced Packaging Systems Symposium
ページ44-47
ページ数4
DOI
出版ステータスPublished - 2013 12 1
イベント2013 6th IEEE Electrical Design of Advanced Packaging Systems Symposium, EDAPS 2013 - Nara, Japan
継続期間: 2013 12 122013 12 15

出版物シリーズ

名前EDAPS 2013 - 2013 IEEE Electrical Design of Advanced Packaging Systems Symposium

Conference

Conference2013 6th IEEE Electrical Design of Advanced Packaging Systems Symposium, EDAPS 2013
国/地域Japan
CityNara
Period13/12/1213/12/15

ASJC Scopus subject areas

  • 電子工学および電気工学

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