Power supply noise evaluation with on-chip noise monitoring for various decoupling schemes of SiP

Takafumi Okumura, Yoshiaki Oizono, Yoshitaka Nabeshima, Toshio Sudo

研究成果

3 被引用数 (Scopus)

抄録

Power integrity design is a critical issue in system-in-packages (SiP's). In particular, power supply disturbance excited by simultaneous switching output (SSO) noise, or core circuits is serious in a 3D stacked die packages. Therefore, decoupling schemes in such SiP's must be carefully designed to reduce the impedance of power distribution network (PDN) as low as possible up to high frequency range and to avoid the parallel resonance occurred by chip-package connection. In this paper, a test chip was designed and fabricated to generate noise and to monitor on-chip power supply noise. Then, a power noise evaluation system has been established. Power supply noise on core circuits was measured with a noise monitoring circuit. The noise on output buffer circuit was measured by a fixed high/low method. Power supply noises were examined in various decoupling schemes. They are with embedded SMD capacitors inside interposer, and SMD capacitors mounted on the backside of interposer along with on-chip capacitance.

本文言語English
ホスト出版物のタイトル2010 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2010
DOI
出版ステータスPublished - 2010 12 1
イベント2010 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2010 - Singapore, Singapore
継続期間: 2010 12 72010 12 9

出版物シリーズ

名前2010 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2010

Conference

Conference2010 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2010
国/地域Singapore
CitySingapore
Period10/12/710/12/9

ASJC Scopus subject areas

  • 電子工学および電気工学

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