Power supply noise has been becoming critical in advanced CMOS digital systems, because power supply noise induces false logic operation and instability. Especially, anti-resonance peaks in power distribution network (PDN) due to the chip-package interaction induce the unwanted power supply fluctuation. In this paper, power supply noises and total impedances of power distribution network (PDN) for the variable structure of on-die capacitances have been examined. In addition, Q factors of anti-resonance peaks for various PDN impedances have been examined by changing the value of on-die capacitance. As a result, it has been proved that Q factors of anti-resonance peaks can be suppressed by increasing on-die capacitance. Furthermore, power supply noise distribution on a chip has been simulated for the various location of noise generating circuits and on-die capacitance.