Signal integrity characterization of high-speed DDR interface

Takuya Kato, Shintaro Yamamoto, Toshio Sudo, Yasushi Ono, Eiji Takahashi, Toru Yamada

研究成果: Conference contribution

2 引用 (Scopus)

抜粋

With the increase of the clock speed of memory systems, signal integrity is becoming more an important design issue to ensure system reliability. DDR2 memory systems adopt on-die termination scheme to reduce reflection noise on a transmission lines. This paper describes a correct prediction method of waveforms at the receiver chip from the waveforms at the vicinity of the packaged chip.

元の言語English
ホスト出版物のタイトル2011 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2011
DOI
出版物ステータスPublished - 2011 12 1
イベント2011 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2011 - Hanzhou, China
継続期間: 2011 12 122011 12 14

出版物シリーズ

名前2011 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2011

Conference

Conference2011 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2011
China
Hanzhou
期間11/12/1211/12/14

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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  • これを引用

    Kato, T., Yamamoto, S., Sudo, T., Ono, Y., Takahashi, E., & Yamada, T. (2011). Signal integrity characterization of high-speed DDR interface. : 2011 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2011 [6213776] (2011 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2011). https://doi.org/10.1109/EDAPS.2011.6213776