@inproceedings{4def6dba54504060bfa915d80f17db81,
title = "Signal integrity characterization of high-speed DDR interface",
abstract = "With the increase of the clock speed of memory systems, signal integrity is becoming more an important design issue to ensure system reliability. DDR2 memory systems adopt on-die termination scheme to reduce reflection noise on a transmission lines. This paper describes a correct prediction method of waveforms at the receiver chip from the waveforms at the vicinity of the packaged chip.",
keywords = "DDR2 memory, S parameter, TDR, signal integrity",
author = "Takuya Kato and Shintaro Yamamoto and Toshio Sudo and Yasushi Ono and Eiji Takahashi and Toru Yamada",
year = "2011",
month = dec,
day = "1",
doi = "10.1109/EDAPS.2011.6213776",
language = "English",
isbn = "9781467322881",
series = "2011 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2011",
booktitle = "2011 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2011",
note = "2011 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2011 ; Conference date: 12-12-2011 Through 14-12-2011",
}