Simulation of recess-structure dependence of gate-lag phenomena in GaAs MESFETs

K. Horio, Y. Mitani, A. Wakabayashi

研究成果: Conference contribution

抄録

We have made two-dimensional simulation of turn-on characteristics of recessed-gate and buried-gate GaAs MESFETs, and studied how the gate-lag or the slow current transient (which may occur due to surface states) is affected by the recess-structural parameters and the off-state gate voltage V Goff. It is shown that when VGoff is around the threshold voltage (pinch-off voltage) Vth, the gate-lag could be greatly reduced by introducing the buried-gate structure. However, it is suggested that large gate-lag might be seen when VGoff is much more negative than Vth.

本文言語English
ホスト出版物のタイトル2001 International Conference on Modeling and Simulation of Microsystems - MSM 2001
編集者M. Laudon, B. Romanowicz
ページ510-513
ページ数4
出版ステータスPublished - 2001 12 1
イベント2001 International Conference on Modeling and Simulation of Microsystems - MSM 2001 - Hilton Head Island, SC, United States
継続期間: 2001 3 192001 3 21

出版物シリーズ

名前2001 International Conference on Modeling and Simulation of Microsystems - MSM 2001

Conference

Conference2001 International Conference on Modeling and Simulation of Microsystems - MSM 2001
国/地域United States
CityHilton Head Island, SC
Period01/3/1901/3/21

ASJC Scopus subject areas

  • 工学(全般)

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