Simulation of surface and buffer trapping effects on gate lag in AlGaN/GaN HEMTs

K. Horio, A. Nakajima, K. Fujii

研究成果: Conference contribution

抄録

Two-dimensional analysis of turn-on characteristics of AlGaN/GaN HEMTs is performed in which both buffer traps and surface states (traps) are considered. It is studied how so-called gate lag is affected by these traps. It is shown that gate lag due to buffer traps can occur because in the off state, electrons are injected into the buffer layer and captured by the traps. It is also shown that gate lag due to an electron-trap-type surface state can occur only when electron's gate tunneling is considered. Dependence of gate lag on buffer-trap parameters is also studied.

本文言語English
ホスト出版物のタイトルNanotechnology 2010
ホスト出版物のサブタイトルElectronics, Devices, Fabrication, MEMS, Fluidics and Computational - Technical Proceedings of the 2010 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2010
ページ693-696
ページ数4
出版ステータスPublished - 2010 11 9
イベントNanotechnology 2010: Electronics, Devices, Fabrication, MEMS, Fluidics and Computational - 2010 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2010 - Anaheim, CA, United States
継続期間: 2010 6 212010 6 24

出版物シリーズ

名前Nanotechnology 2010: Electronics, Devices, Fabrication, MEMS, Fluidics and Computational - Technical Proceedings of the 2010 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2010
2

Conference

ConferenceNanotechnology 2010: Electronics, Devices, Fabrication, MEMS, Fluidics and Computational - 2010 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2010
国/地域United States
CityAnaheim, CA
Period10/6/2110/6/24

ASJC Scopus subject areas

  • ハードウェアとアーキテクチャ
  • 電子工学および電気工学

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