SLD-1(Silent Large Datapath): A ultra low power reconfigurable accelerator

Nobuaki Ozaki, Kimiyoshi Usami, Hideharu Amano, Mitaro Namiki, Hiroshi Nakamura, Masaaki Kondo

研究成果: Conference contribution

2 引用 (Scopus)

抜粋

SLD(Silent Large Datapath)-1 is a prototype accelerator for media processing consisting of a large Processing Element (PE) array which includes 24bit 8 × 8 PEs with combinatorial circuits and a small micro-controller for data memory access. It was fabricated in 2.1mm 4.2mm × 65 nm CMOS, and achieves 1.356GOPS/11mW sustained performance by reducing overhead of clock tree and the benefit of voltage scaling.

元の言語English
ホスト出版物のタイトルIEEE Symposium on Low-Power and High-Speed Chips - 2011 IEEE COOL Chips XIV, Proceedings
DOI
出版物ステータスPublished - 2011 7 18
イベント14th IEEE Symposium on Low-Power and High-Speed Chips, COOL Chips XIV - Yokohama, Japan
継続期間: 2011 4 202011 4 22

出版物シリーズ

名前IEEE Symposium on Low-Power and High-Speed Chips - 2011 IEEE COOL Chips XIV, Proceedings

Conference

Conference14th IEEE Symposium on Low-Power and High-Speed Chips, COOL Chips XIV
Japan
Yokohama
期間11/4/2011/4/22

    フィンガープリント

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

これを引用

Ozaki, N., Usami, K., Amano, H., Namiki, M., Nakamura, H., & Kondo, M. (2011). SLD-1(Silent Large Datapath): A ultra low power reconfigurable accelerator. : IEEE Symposium on Low-Power and High-Speed Chips - 2011 IEEE COOL Chips XIV, Proceedings [5890918] (IEEE Symposium on Low-Power and High-Speed Chips - 2011 IEEE COOL Chips XIV, Proceedings). https://doi.org/10.1109/COOLCHIPS.2011.5890918