Sleep transistor sizing method using accurate delay estimation considering input vector pattern and non-linear current model

Mathematics

• Delay Estimation 100%
• Sleep 77%
• Leakage 19%
• Model 17%
• High Accuracy 15%
• Logic 11%
• Circuit Design 11%
• Degradation 9%
• Insertion 8%
• Experimental Results 7%
• Module 5%
• Simulation 4%
• Performance 4%

Engineering & Materials Science

• Sleep 55%
• Transistors 44%
• Networks (circuits) 16%
• Logic gates 8%
• Degradation 5%