A novel design technique which combines a Variable Supply-voltage scheme and a Clustered Voltage Scaling is presented (VS-CVS scheme). A theory to choose the optimum supply voltages in the VS-CVS scheme is discussed which enables us to perform chip design in a top-down fashion. Level-shifting flip-flops are developed which reduce power, delay, area penalties significantly. Application of this technique to an MPEG4 video codec saves 55% of the power dissipation without degrading circuit, performance compared to a conventional CMOS design.
|ジャーナル||Proceedings of the Custom Integrated Circuits Conference|
|出版ステータス||Published - 1998 1月 1|
|イベント||Proceedings of the 1998 IEEE Custom Integrated Circuits Conference - Santa Clara, CA, USA|
継続期間: 1998 5月 11 → 1998 5月 14
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