Top-down low power design technique using clustered voltage scaling with variable supply-voltage scheme

Mototsugu Hamada, Masafumi Takahashi, Hideho Arakida, Akihiko Chiba, Toshihiro Terazawa, Takashi Ishikawa, Masahiro Kanazawa, Mutsunori Igarashi, Kimiyoshi Usami, Tadahiro Kuroda

研究成果: Conference article

79 引用 (Scopus)

抜粋

A novel design technique which combines a Variable Supply-voltage scheme and a Clustered Voltage Scaling is presented (VS-CVS scheme). A theory to choose the optimum supply voltages in the VS-CVS scheme is discussed which enables us to perform chip design in a top-down fashion. Level-shifting flip-flops are developed which reduce power, delay, area penalties significantly. Application of this technique to an MPEG4 video codec saves 55% of the power dissipation without degrading circuit, performance compared to a conventional CMOS design.

元の言語English
ページ(範囲)495-498
ページ数4
ジャーナルProceedings of the Custom Integrated Circuits Conference
出版物ステータスPublished - 1998 1 1
イベントProceedings of the 1998 IEEE Custom Integrated Circuits Conference - Santa Clara, CA, USA
継続期間: 1998 5 111998 5 14

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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  • これを引用

    Hamada, M., Takahashi, M., Arakida, H., Chiba, A., Terazawa, T., Ishikawa, T., Kanazawa, M., Igarashi, M., Usami, K., & Kuroda, T. (1998). Top-down low power design technique using clustered voltage scaling with variable supply-voltage scheme. Proceedings of the Custom Integrated Circuits Conference, 495-498.