Two-dimensional analysis of gate-lag phenomena in recessed-gate GaAs MESFETs

K. Horio, T. Yamada

研究成果: Paper

抜粋

Effects of surface states on turn-on characteristics of recessed-gate GaAs MESFETs are studied by two-dimensional simulation. It is found that the recess depth dr is deep and the distance between the gate and the recess edge Lr is set to be very narrow, the gate-lag (slow current transient) extinguishes for a case with surface states considered on horizontal planes only. However, in a realistic case with surface states included on both horizontal and vertical planes, the gate-lag is not eliminated even if dr is made rather deep. This is attributed to the fact that when the deep-acceptor-like surface state acts as a hole trap, the thickness of surface depletion layer can change much by the applied gate bias. To eliminate the gate-lag, the deep acceptor should be made electron-trap type. This can be realized by reducing the surface state density.

元の言語English
ページ7-12
ページ数6
出版物ステータスPublished - 1997 12 1
イベントProceedings of the 1997 Workshop on High Performance Electron Devices for Microwave and Optoelectronic Applications, EDMO - London, UK
継続期間: 1997 11 241997 11 25

Other

OtherProceedings of the 1997 Workshop on High Performance Electron Devices for Microwave and Optoelectronic Applications, EDMO
London, UK
期間97/11/2497/11/25

ASJC Scopus subject areas

  • Engineering(all)

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  • これを引用

    Horio, K., & Yamada, T. (1997). Two-dimensional analysis of gate-lag phenomena in recessed-gate GaAs MESFETs. 7-12. 論文発表場所 Proceedings of the 1997 Workshop on High Performance Electron Devices for Microwave and Optoelectronic Applications, EDMO, London, UK, .