Two-dimensional analysis of surface-state effects on turn-on characteristics in GaAs MESFET's

Kazushige Horio, Tomiko Yamada

研究成果: Article査読

57 被引用数 (Scopus)

抄録

Surface-state effects on gate-lag or slow current transient in GaAs MESFET's are studied by two-dimensional (2-D) simulation. It is shown that the gate-lag becomes remarkable when the deep-acceptor surface state acts as a hole trap. To suppress it, the deep acceptor should be made electron-trap-like, which can be realized by reducing the surface-state density. Device structures expected to have less gate-lag, such as a self-aligned structure with n+ source and drain regions and a recessed-gate structure are also analyzed. An analysis of the possible complete elimination of gate-lag in these structures is given.

本文言語English
ページ(範囲)648-655
ページ数8
ジャーナルIEEE Transactions on Electron Devices
46
4
DOI
出版ステータスPublished - 1999 1 1

ASJC Scopus subject areas

  • 電子材料、光学材料、および磁性材料
  • 電子工学および電気工学

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