Surface-state effects on gate-lag or slow current transient in GaAs MESFET's are studied by two-dimensional (2-D) simulation. It is shown that the gate-lag becomes remarkable when the deep-acceptor surface state acts as a hole trap. To suppress it, the deep acceptor should be made electron-trap-like, which can be realized by reducing the surface-state density. Device structures expected to have less gate-lag, such as a self-aligned structure with n+ source and drain regions and a recessed-gate structure are also analyzed. An analysis of the possible complete elimination of gate-lag in these structures is given.
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