Ultra-high-speed and universal-coding-rate Viterbi decoder VLSIC-SNUFEC VLSI

Katsuhiko Kawazoe, Shunji Honda, Shuji Kubota, Shuzo Kato

研究成果: Conference contribution

3 被引用数 (Scopus)

抄録

An Ultra-high-speed (higher than 60Mbps) Viterbi decoder VLSIC with coding rates from one-half to fifteen-sixteenth and a constraint length of seven for forward error correction (FEC) has been developed using 0.8-μm semi-custom CMOS LSIC technology. To reduce the power consumption of the one-chip high-coding-rate Viterbi decoder, a newly developed universal-coding-rate scarce-state-transition (SST) Viterbi decoding scheme and low-power-consumption burst-mode-selection (BMS) path memory have been employed. In addition, a new maximum-likelihood-decision (MLD) circuit of the SST Viterbi decoder has been developed to reduce the path memory length without coding-gain degradation. The developed Viterbi decoder VLSIC achieves a maximum data rate of 60Mbps with a power consumption of 2.5W and achieves near theoretical net coding-gain performance for various coding rates.

本文言語English
ホスト出版物のタイトルIEEE International Conference on Communications
出版社Publ by IEEE
ページ1434-1438
ページ数5
ISBN(印刷版)0780309510
出版ステータスPublished - 1993 1 1
外部発表はい
イベントProceedings of the IEEE International Conference on Communications '93 - Geneva, Switz
継続期間: 1993 5 231993 5 26

出版物シリーズ

名前IEEE International Conference on Communications

Other

OtherProceedings of the IEEE International Conference on Communications '93
CityGeneva, Switz
Period93/5/2393/5/26

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Electrical and Electronic Engineering

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