Ultra-high-speed and universal-coding-rate Viterbi decoder VLSIC - SNUFEC VLSI

Katsuhiko Kawazoe, Shunji Honda, Shuji Kubota, Shuzo Kato

研究成果: Article査読

5 被引用数 (Scopus)

抄録

An Ultra-high-speed (higher than 60 MHz) Viterbi decoder VLSIC with coding rates from one-half to fifteen-sixteenth and a constraint length of seven for forward error correction (FEC) has been developed using 0.8-μm semi-custom CMOS LSIC technology and a newly developed high-speed ACS circuit. To reduce power consumption of the one-chip Viterbi decoder, a universal-coding-rate scarce-state-transition (SST) Viterbi decoding scheme and low-power-consumption burst-mode-selection (BMS) path memory have been proposed and employed to the developed VLSIC. In addition, a new maximum-likelihood-decision (MLD) circuit for the SST Viterbi decoder has been developed. The total power consumption of the developed chip is reduced to 75% of the conventional one and the developed Viterbi decoder VLSIC achieves a maximum operation speed of 60 MHz. It achieves near theoretical net coding-gain performance for various coding rates.

本文言語English
ページ(範囲)1888-1894
ページ数7
ジャーナルIEICE Transactions on Electronics
E77-C
12
出版ステータスPublished - 1994 12 1
外部発表はい

ASJC Scopus subject areas

  • 電子材料、光学材料、および磁性材料
  • 電子工学および電気工学

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