Ultra-low-power-consumption high-speed GaAs 256/258 dual-modulus prescaler IC

T. Maeda, Sh Wada, M. Tokushima, M. Ishikawa, J. Yamazaki, M. Fujii

研究成果: Paper

3 引用 (Scopus)

抜粋

This paper describes a GaAs divide-by-256/258 dual-modulus static prescaler IC. The prescaler has a pulse swallow counter-type architecture and quasi-differential switch flip-flop (QD-FF) as its basic circuit architecture. For the input buffer circuit, we have developed a circuit that we call a source coupled push-pull circuit (SCC), which can generate high-frequency complementary signals from a single phase signal at a low supply voltage. The IC operates at up to 14.5 GHz with a power consumption of 22 mW. The power consumption is 1/100 that of a previously reported prescaler.

元の言語English
ページ[d]175-178
出版物ステータスPublished - 1997 12 1
イベントProceedings of the 1997 19th Annual IEEE Gallium Arsenide Integrated Circuit Symposium - Anaheim, CA, USA
継続期間: 1997 10 121997 10 15

Other

OtherProceedings of the 1997 19th Annual IEEE Gallium Arsenide Integrated Circuit Symposium
Anaheim, CA, USA
期間97/10/1297/10/15

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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  • これを引用

    Maeda, T., Wada, S., Tokushima, M., Ishikawa, M., Yamazaki, J., & Fujii, M. (1997). Ultra-low-power-consumption high-speed GaAs 256/258 dual-modulus prescaler IC. [d]175-178. 論文発表場所 Proceedings of the 1997 19th Annual IEEE Gallium Arsenide Integrated Circuit Symposium, Anaheim, CA, USA, .