Very low power consumption Viterbi decoder LSlC employing the SST (scarce state transition) scheme for multimedia mobile communications

K. Seki, S. Kubota, M. Mizoguchi, S. Kato

研究成果: Article査読

15 被引用数 (Scopus)

抄録

A very low power consumption Viterbi decoder LSIC has been developed by using a low supply voltage 0.8 μm CMOS masterslice process technology. By employing the scarce state transition (SST) scheme, this LSIC achieves a drastic reduction in power consumption below 600 μW at a supply voltage of 1V when the data rate is 1152 kbit/s and the bit error rate is less than 10-3. This excellent performance has paved the way to employing the strong forward error correction and low power consumption portable terminals for personal communications, mobile multimedia communications, and digital and audio broadcasting.

本文言語English
ページ(範囲)637-639
ページ数3
ジャーナルElectronics Letters
30
8
DOI
出版ステータスPublished - 1994 1 1
外部発表はい

ASJC Scopus subject areas

  • 電子工学および電気工学

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